Architecting Effectual Computation for Machine Learning Accelerators

Published in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2019

Recommended citation: Architecting Effectual Computation for Machine Learning Accelerators. Hang Lu, Mingzhe Zhang, Yinhe Han, Huawei Li, Li Xiaowei. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD).

Abstract

Inference efficiency is the predominant design consideration for modern machine learning accelerators. The ability of executing multiply-and-accumulate (MAC) significantly impacts the throughput and energy consumption during inference. However, MAC operation suffers from significant ineffectual computations that severely undermines the inference efficiency and must be appropriately handled by the accelerator. The ineffectual computations are manifested in two ways: firstly, zero values as the input operands of the multiplier, waste time and energy but contribute nothing to the model inference; secondly, zero bits in non-zero values occupy a large portion of multiplication time but are useless to the final result. In this article, we propose an ineffectual-free yet cost-effective computing architecture, called Split-and-ACcumulate (SAC) with two essential bit detection mechanisms to address these intractable problems in tandem. It replaces the conventional MAC operation in the accelerator by only manipulating the essential bits in the parameters (weights) to accomplish the partial sum computation. Besides, it also eliminates multiplications without any accuracy loss, and supports a wide range of precision configurations. Based on SAC, we propose an accelerator family called Tetris and demonstrate its application in accelerating state-of-the-art deep learning models. Tetris includes two implementations designed for either high performance (i.e. cloud applications) or low power consumption (i.e. edge devices) respectively, contingent to its built-in essential bit detection mechanism. We evaluate our design with Vivado HLS platform and achieve up to 6.96x performance enhancement, and up to 55.1x energy efficiency improvement over conventional accelerator designs.